The present disclosure is related to lithography, and more particularly to the design of a charged particle beam writer system and methods for using the charged particle beam writer system to manufacture a surface which may be a reticle, a wafer, or any other surface.
In the production or manufacturing of semiconductor devices, such as integrated circuits, optical lithography may be used to fabricate the semiconductor devices. Optical lithography is a printing process in which a lithographic mask or photomask manufactured from a reticle is used to transfer patterns to a substrate such as a semiconductor or silicon wafer to create the integrated circuit. Other substrates could include flat panel displays or even other reticles. Also, extreme ultraviolet (EUV) or X-ray lithography are considered types of optical lithography. The reticle or multiple reticles may contain a circuit pattern corresponding to an individual layer of the integrated circuit, and this pattern can be imaged onto a certain area on the substrate that has been coated with a layer of radiation-sensitive material known as photoresist or resist. Once the patterned layer is transferred the layer may undergo various other processes such as etching, ion-implantation (doping), metallization, oxidation, and polishing. These processes are employed to finish an individual layer in the substrate. If several layers are required, then the whole process or variations thereof will be repeated for each new layer. Eventually, a combination of multiples of devices or integrated circuits will be present on the substrate. These integrated circuits may then be separated from one another by dicing or sawing and then may be mounted into individual packages. In the more general case, the patterns on the substrate may be used to define artifacts such as display pixels, holograms or magnetic recording heads.
In the production or manufacturing of semiconductor devices, such as integrated circuits, maskless direct write may also be used to fabricate the semiconductor devices. Maskless direct write is a printing process in which charged particle beam lithography is used to transfer patterns to a substrate such as a semiconductor or silicon wafer to create the integrated circuit. Other substrates could include flat panel displays, imprint masks for nano-imprinting, or even reticles. Desired patterns of a layer are written directly on the surface, which in this case is also the substrate. Once the patterned layer is transferred the layer may undergo various other processes such as etching, ion-implantation (doping), metallization, oxidation, and polishing. These processes are employed to finish an individual layer in the substrate. If several layers are required, then the whole process or variations thereof will be repeated for each new layer. Some of the layers may be written using optical lithography while others may be written using maskless direct write to fabricate the same substrate. Eventually, a combination of multiples of devices or integrated circuits will be present on the substrate. These integrated circuits are then separated from one another by dicing or sawing and then mounted into individual packages. In the more general case, the patterns on the surface may be used to define artifacts such as display pixels, holograms or magnetic recording heads.
As indicated, in optical lithography the lithographic mask or reticle comprises geometric patterns corresponding to the circuit components to be integrated onto a substrate. The patterns used to manufacture the reticle may be generated utilizing computer-aided design (CAD) software or programs. In designing the patterns the CAD program may follow a set of predetermined design rules in order to create the reticle. These rules are set by processing, design, and end-use limitations. An example of an end-use limitation is defining the geometry of a transistor in a way in which it cannot sufficiently operate at the required supply voltage. In particular, design rules can define the space tolerance between circuit devices or interconnect lines. The design rules are, for example, used to ensure that the circuit devices or lines do not interact with one another in an undesirable manner. For example, the design rules are used so that lines do not get too close to each other in a way that may cause a short circuit. The design rule limitations reflect, among other things, the smallest dimensions that can be reliably fabricated. When referring to these small dimensions, one usually introduces the concept of a critical dimension. These are, for instance, defined as the smallest width of a line or the smallest space between two lines, those dimensions requiring exquisite control.
One goal in integrated circuit fabrication by optical lithography is to reproduce on the substrate the original circuit design by use of the reticle. Integrated circuit fabricators are always attempting to use the semiconductor wafer real estate as efficiently as possible. Engineers keep shrinking the size of the circuits, either allowing an integrated circuit with the same number of circuit elements to be smaller and use less power, or allowing an integrated circuit of the same size to contain more circuit elements. As the size of an integrated circuit critical dimension is reduced and its circuit density increases, the critical dimension of the circuit pattern or physical design approaches the resolution limit of the optical exposure tool used in optical lithography. As the critical dimensions of the circuit pattern become smaller and approach the resolution value of the exposure tool, the accurate transcription of the physical design to the actual circuit pattern developed on the resist layer becomes difficult. To further the use of optical lithography to transfer patterns having features that are smaller than the light wavelength used in the optical lithography process, a process known as optical proximity correction (OPC) has been developed. OPC alters the physical design to compensate for distortions caused by effects such as optical diffraction and the optical interaction of features with proximate features. OPC includes all resolution enhancement technologies performed with a reticle.
OPC may add sub-resolution lithographic features to mask patterns to reduce differences between the original physical design pattern, that is, the design, and the final transferred circuit pattern on the substrate. The sub-resolution lithographic features interact with the original patterns in the physical design and with each other and compensate for proximity effects to improve the final transferred circuit pattern. One feature that is used to improve the transfer of the pattern is a sub-resolution assist feature (SRAF). Another feature that is added to improve pattern transference is referred to as “serifs”. Serifs are small features that can be positioned on a corner of a pattern to sharpen the corner in the final transferred image. It is often the case that the precision demanded of the surface manufacturing process for SRAFs is less than that for patterns that are intended to print on the substrate, often referred to as main features. Serifs are a part of a main feature. As the limits of optical lithography are being extended far into the sub-wavelength regime, the OPC features must be made more and more complex in order to compensate for even more subtle interactions and effects. As imaging systems are pushed closer to their limits, the ability to produce reticles with sufficiently fine OPC features becomes critical. Although adding serifs or other OPC features to a mask pattern is advantageous, it also substantially increases the total feature count in the mask pattern. For example, adding a serif to each of the corners of a square using conventional techniques adds eight more rectangles to a mask or reticle pattern. Adding OPC features is a very laborious task, requires costly computation time, and results in more expensive reticles. Not only are OPC patterns complex, but since optical proximity effects are long range compared to minimum line and space dimensions, the correct OPC patterns in a given location depend significantly on what other geometry is in the neighborhood. Thus, for instance, a line end will have different size serifs depending on what is near it on the reticle. This is even though the objective might be to produce exactly the same shape on the wafer. It is conventional to discuss the OPC-decorated patterns to be written on a reticle in terms of main features, that is features that reflect the design before OPC decoration, and OPC features, where OPC features might include serifs, jogs, and SRAF. To quantify what is meant by slight variations, a typical slight variation in OPC decoration from neighborhood to neighborhood might be 5% to 80% of a main feature size. Note that for clarity, variations in the design of the OPC are what is being referenced. Manufacturing variations, such as line-edge roughness and corner rounding, will also be present in the actual surface patterns. When these OPC variations produce substantially the same patterns on the wafer, what is meant is that the geometry on the wafer is targeted to be the same within a specified error, which depends on the details of the function that that geometry is designed to perform, e.g., a transistor or a wire. Nevertheless, typical specifications are in the 2%-50% of a main feature range. There are numerous manufacturing factors that also cause variations, but the OPC component of that overall error is often in the range listed. OPC shapes such as sub-resolution assist features are subject to various design rules, such as a rule based on the size of the smallest feature that can be transferred to the wafer using optical lithography. Other design rules may come from the mask manufacturing process or, if a character projection charged particle beam writing system is used to form the pattern on a reticle, from the stencil manufacturing process. It should also be noted that the accuracy requirement of the SRAF features on the mask may be lower than the accuracy requirements for the main features on the mask.
Inverse lithography technology (ILT) is one type of OPC technique. ILT is a process in which a pattern to be formed on a reticle is directly computed from a pattern which is desired to be formed on a substrate such as a silicon wafer. This may include simulating the optical lithography process in the reverse direction, using the desired pattern on the surface as input. ILT-computed reticle patterns may be purely curvilinear—i.e. completely non-rectilinear—and may include circular, nearly circular, annular, nearly annular, oval and/or nearly oval patterns. Since curvilinear patterns are difficult and expensive to form on a reticle using conventional techniques, rectilinear approximations of the curvilinear patterns may be used. In this disclosure ILT, OPC, source mask optimization (SMO), and computational lithography are terms that are used interchangeably.
As the minimum feature size decreases along Moore's Law, and especially as features with dimensions less than 50 nm on the substrate are formed using optical lithography with a 193 nm illumination source with immersion technology, the OPC features on a photomask become very complex in shape. Specifically, it will not be practical to limit the shapes on a reticle to orthogonal and rectilinear shapes and still achieve a wafer fabrication process window sufficient to produce an acceptable process yield.
There are a number of technologies used for forming patterns on a reticle, including using optical lithography or charged particle beam systems. The most commonly used system is the variable shape beam (VSB) type, where a precise electron beam is shaped and steered onto a resist-coated surface of the reticle. These shapes are simple shapes, usually limited to rectangles of certain minimum and maximum sizes and triangles with their three internal angles being 45 degrees, 45 degrees, and 90 degrees of certain minimum and maximum sizes. The sides of the rectangles and the legs of the right triangles are parallel to the X, Y axes. At pre-determined locations, doses of electrons are shot into the resist with these simple shapes. The total writing time for this type of system increases with the number of shots. A second type of system is a character projection system, referred to as CP in this disclosure. In this case there is a stencil in the system that has in it a variety of shapes which may be rectilinear, arbitrary-angled linear, circular, annular, part circular, part annular, or arbitrary curvilinear shapes, and may be a connected set of complex shapes or a group of disjointed sets of a connected set of complex shapes. An electron beam can be shot through the stencil to efficiently produce more complex patterns (i.e. CP characters, sometimes referred to as characters) on the reticle. In theory, such a system could be faster than a VSB system because it can shoot more complex shapes with each time-consuming shot. There is currently, however, no CP electron beam writer system available for forming patterns on a reticle.
A shot comprises all the necessary instructions to specify which part of which character or VSB second aperture is to be shot at what location on the surface with what dose and what magnification. The instructions needed may take many forms, for example in a form directly corresponding to instructions for the charged particle beam writing system, such as deflection specifications of the various electrostatic or electromagnetic deflection shields. In other instances, the instructions may take the form of geometric descriptions of the desired shapes on the surface. In yet other circumstances, it may take the form of any other encoding which is sufficient to derive the required VSB, CP, or partial projection of a CP character with or without a specified dose, and with or without a specified magnification factor.
The use of VSB electron beam systems to form curvilinear patterns on a reticle with high fidelity is expensive, because a very large number of VSB shots are required to form the curvilinear shapes. Conventionally, reducing the VSB shot count results in lowering the fidelity of the curvilinear patterns that are formed, causing the patterns to become bumpier, meaning less smooth.
Thus, it would be advantageous to reduce the time and expense it takes to prepare and manufacture a reticle that is used for a substrate. More generally, it would be advantageous to reduce the time and expense it takes to prepare and manufacture any surface.